Omega-vehicle-security OME-PIO-D56 User Manual

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I/O select (Sec. 3.3.7) disable\ input Latch Clock input D/O latch CKT RESET\ (Sec. 3.3.1) Data (Sec. 3.3.8) D/I/O d

2.3.2 DI Port Architecture (CON2) When the PC is powered up, all DI (CON2) port operations are disabled. The RESET\ signal controls the enable/disa

2.3.3 DO Port Architecture (CON1) When the PC is powered up, all DO port (CON1) operations are disabled. The RESET\ signal controls the enable/disa

2.4 Interrupt Operation All PC0, PC1, PC2 and PC3 can be used as an interrupt signal sources. Refer to Sec. 2.1 for PC0/PC1/PC2/PC3 location. The

2.4.1 Interrupt Block Diagram of OME-PIO-D56/D24 INT_CHAN_0INT_CHAN_1INT_CHAN_2INT_CHAN_3INT\Level_triggerinitial_lowactive_high The

2.4.2 INT_CHAN_0/1/2/3 INT_CHAN_0 (1/2/3)Inverted/Noninverted selectINV0(1/2/3)Enable/Disable selectEN0(1/2/3)PC0(PC1/PC2/PC3) The INT

2.4.3 Initial_high, active_low Interrupt source If the PC0 is a initial_high, active_low signal, the interrupt service routine should use INV0 to i

2.4.4 Initial_low, active_high Interrupt source If the PC0 is a initial_low, active_high signal, the interrupt service routine should use INV0 to i

2.4.5 Muliti-Interrupt Source Assume: PC0 is initial Low, active High, PC1 is initial High, active Low

void interrupt irq_service() { new_int_state=inportb(wBase+7)&0x0f; /* read all interrupt state */ int_c=new_int_state^now_int_state; /* compa

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2.5 Daughter Boards 2.5.1 OME-DB-37 The OME-DB-37 is a general purpose daughter board for D-sub 37 pins, designed for an easy-wiring connection

2.5.4 OME-ADP-20/PCI The OME-ADP-20/PCI is an extender for 20-pin header. One side of OME-ADP-20/PCI connects to a 20-pin header. The other side m

2.5.5 OME-DB-24PD Isolated Input Board The OME-DB-24PD is a 24 channel isolated digital input daughter board. The optically isolated inputs of the

2.5.6 OME-DB-24RD Relay Board The OME-DB-24RD, a 24 channel relay output board, consists of 24 form C relays for efficient, programmable load switc

2.5.7 OME-DB-24PRD, OME-DB-24POR, OME-DB-24C OME-DB-24PRD 24*power relay, 5A/250V OME-DB-24POR 24*photo MOS relay, 0.1A/350VAC OME-DB-24C 24*op

2.5.8 Daughter Board Comparison Table 20-pin flat-cable 50-pin flat-cable D-sub 37-pin OME-DB-37 No No Yes OME-DN-37 No No Yes OME-ADP-37/

2.6 Pin Assignment CON3: 37 pin of D-type female connector. Pin Number Description Pin Number Description 1 N.C. 20 VCC 2 N.C. 21 GND 3 P1B7 22

CON2 : 20-pin header (only for OME-PIO-D56) Pin Number Description Pin Number Description 1 DI0 2 DI1 3 DI2 4 DI3 5 DI4 6 DI5 7 DI6 8 DI7 9 DI8

3. I/O Control Register 3.1 How to Find the I/O Address The plug & play BIOS will assign a proper I/O address to every OME-PIO/PISO series

3.1.1 PIO_DriverInit PIO_DriverInit(&wBoards, wSubVendor,wSubDevice,wSubAux) • wBoards=0 to N Æ number of boards found in this PC • wSubV

OME-PIO-D56/D24 User Manual OME-PIO-D56/OME-PIO-D24 User Manual (Ver.2.1, Oct/2003) ----

Sample program 2: find all OME-PIO/PISO in this PC (refer to Sec. 4.1 for more information) wRetVal=PIO_DriverInit(&wBoards,0xff,0xff,0xff); /*fi

The sub-IDs of OME-PIO/PISO series card are given as following: OME-PIO/PISO series card Description Sub_vendor Sub_device Sub_AUX OME-PIO-D144 (Rev

3.1.2 PIO_GetConfigAddressSpace PIO_GetConfigAddressSpace(wBoardNo,*wBase,*wIrq, *wSubVendor, *wSubDevice,*wS

3.1.3 Show_PIO_PISO Show_PIO_PISO(wSubVendor,wSubDevice,wSubAux) • wSubVendor Æ subVendor ID of board to find • wSubDevice Æ subDevice ID of bo

3.2 The Assignment of I/O Address The plug & play BIOS will assign the proper I/O address to the OME-PIO/PISO series card. If there is only one

3.3 The I/O Address Map The I/O address of OME-PIO/PISO series card is automatically assigned by the main board ROM BIOS. The I/O address can also

3.3.1 RESET\ Control Register (Read/Write): wBase+0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved Reserved Reserved Reserved Res

3.3.4 INT Mask Control Register (Read/Write): wBase+5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 EN3 EN2 EN1 EN0 Note. Refer t

3.3.6 Interrupt Polarity Control Register (Read/Write): wBase+0x2A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 INV3 INV2 INV1 I

3.3.8 Read/Write 8-bit data Register (Read/Write):wBase+0xc0/0xc4/0xc8/0xd0/0xd4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D7 D6 D5 D

Table of Contents 1. INTRODUCTION...

4. Demo program It is recommended to read the release notes first. Important information will be given in release note as follows: 1. Where you ca

4.1 PIO_PISO /* ------------------------------------------------------------ */ /* Find all PIO_PISO series cards in this PC system */

4.1.1 PIO_PISO.EXE for Windows User can find this utility in the company CD or floppy disk. It is useful for all OME-PIO/PISO series card.

4.2 DEMO1 /* demo 1 : D/O demo of CON3 */ /* step 1 : connect a OME-DB-24C to CON3 of OME-PIO-D56/D24 */

4.3 DEMO2 /* demo 2 : DI/O demo of CON1, CON2 & CON3 */ /* step 1 : connect OME-DB-24P to CON3 of OME-PIO-D56/D24

4.4 DEMO3 /* demo 3 : Count high pulse of PC0 */ /* (initial Low & active High)

irqmask=inportb(A1_8259+1); outportb(A1_8259+1,irqmask & 0xff ^ (1<<wIrq)); setvect(wIrq+8,irq_service); } else { irqmask=

4.5 DEMO4 /* demo 4 : Count high pulse of PC0 */ /* (initial High & active Low)

} else { irqmask=inportb(A1_8259+1); outportb(A1_8259+1,irqmask & 0xfb); /* IRQ2 */ irqmask=inportb(A2_8259+1);

4.6 DEMO5 /* demo 5 : Four interrupt source */ /* PC0 : initial Low , active High */

1. Introduction The OME-PIO-D56/OME-OME-PIO-D24 provides 56/24 TTL digital I/O lines. The OME-PIO-D56/OME-OME-PIO-D24 consists of one 24-bit bi-dir

if (wIrq<8) { irqmask=inportb(A1_8259+1); outportb(A1_8259+1,irqmask & 0xff ^ (1<<wIrq)); setvect(wIrq+8,irq_service); } e

OME-PIO-D56/OME-PIO-D24 User Manual (Ver.2.1, Oct/2003) ---- 49 else /* now PC1 is change to low */ {

WARRANTY/DISCLAIMEROMEGA ENGINEERING, INC. warrants this unit to be free of defects in materials and workmanship for aperiod of 13 months from date of

M4038/0104Where Do I Find Everything I Need for Process Measurement and Control? OMEGA…Of Course!Shop online at www.omega.comTEMPERATUREThermocouple

1.2 Specifications • All inputs are TTL compatible Logic high voltage : 2.4V (Min.) Logic low voltage : 0.8V (Max.) • All outputs are TTL compa

1.4 PCI Data Acquisition Family We provide a family of PCI bus data acquisition cards. These cards can be divided into three groups as follows: 1.

2. Hardware configuration 2.1 Board Layout CON1CON2CON3PCI BUSPIO-D56 PIO-D24121920121920D/ID/ODI/OPort0Port1Port2only for PIO-D56 OME-PIO-

2.2 I/O Port Location The OME-PIO-D56/OME-PIO-D24 consists of one 24-bit bi-directional port, one 16 bit input port and one 16 bit output port